FinFET (2011–2025)

• Gate wraps around three sides of a fin-shaped channel
• Dominated from 16nm through 3nm
• Running out of scaling room — leakage increases, control weakens

GAA Nanosheet (N2+)

• Gate wraps around all four sides of stacked nanosheets
• Superior electrostatic control — less leakage
• Tunable channel widths for performance/power tradeoff
• Enables continued scaling below 3nm

Wafer cost by node

Chip design costs

A single 2nm fab costs ~$28 billion for ~50,000 wafer starts per month, plus $1.5–2B in annual operating costs.

TSMC is planning 3–5% price hikes for sub-5nm nodes in 2026 — customers have no alternative.

• 100% market share in EUV lithography — no competitor exists
• 30+ years of R&D to develop EUV (started in the 1990s)
• Nikon and Canon gave up on EUV around 2009 — too hard, too expensive
• Each EUV machine contains 100,000+ components from hundreds of suppliers
• Weighs ~165 tons, ships in 40+ containers
• Critical dependency on Carl Zeiss SMT for irreplaceable precision mirror optics

• EUV uses 13.5nm wavelength light (extreme ultraviolet) to print circuit patterns
• Previous gen (DUV) used 193nm light — EUV is 14× shorter wavelength
• Shorter wavelength = finer features can be printed
• EUV light is generated by firing a high-power laser at tin droplets 50,000 times per second
• The resulting plasma emits EUV photons
• Photons are collected by ultra-precise multi-layer mirrors (Carl Zeiss)
• The entire light path must be in a near-perfect vacuum — air absorbs EUV

• Numerical aperture (NA): from 0.33 (Low-NA) to 0.55 (High-NA)
• Higher NA = finer resolution, essential for sub-2nm nodes
• Without High-NA, you need DUV multi-patterning (many more steps, lower yield)

The machines

• EXE:5000 (1st gen): 3 units shipped for R&D. Intel has two in Oregon.
• EXE:5200B (2nd gen, production model): 60% more productive. 175–200 wafers/hour. First delivered Q2 2025.
• Intel completed installation and acceptance of EXE:5200B in Dec 2025 for its 14A (1.4nm) node

• TSMC’s 2.5D advanced packaging technology
• Uses a silicon interposer to connect multiple chiplets (GPU die + HBM stacks) in a single package
• Ultra-high bandwidth interconnects between GPU and memory

Two main variants

• CoWoS-S: Silicon interposer. Used for A100, H100.
• CoWoS-L: Local silicon interconnect bridges + organic interposer. Used for B200, B300. Supports larger packages.

TSMC CEO C.C. Wei: “Our CoWoS capacity is very tight and remains sold out through 2025 and into 2026.”

Even with aggressive expansion, a significant supply-demand gap persists. TSMC is outsourcing 240–270K wafers annually to Amkor and SPIL.

of the world’s most advanced chips (sub-10nm) are manufactured in Taiwan

• TSMC’s most advanced node (2nm) is produced only in Taiwan
• 2nm won’t be produced in Arizona until 2028 at earliest
• Taiwan prohibits overseas production of its most advanced semiconductors as a “silicon shield”

Of $33.7B allocated, only $6B actually disbursed by mid-2025. Milestone-based — companies front costs first.

Japan — the quiet success

• TSMC Kumamoto (JASM): Fab 1 operational since late 2024 (12/16nm). Fab 2 upgraded from 6nm to 3nm (possibly 2nm), mass production late 2027.
• Rapidus (Hokkaido): 2nm pilot line operational since April 2025. Using High-NA EUV. Trial production target: April 2026.

Europe

• TSMC Dresden (ESMC): 28/22nm and 16/12nm. Equipment move-in H2 2026, production 2027.
• Intel Magdeburg: Cancelled. EU planning “Chips Act 2.0” in response.

• SMIC uses Self-Aligned Quadruple Patterning (SAQP) — printing the same layer 4+ times
• At 5nm: may require Self-Aligned Octuple Patterning (SAOP) — 8 passes per layer
• Each pass adds cost, time, and yield risk
• Result: 40–50% higher cost per wafer than EUV-based equivalent

What China cannot get

• EUV machines — any type (banned since 2019)
• Advanced DUV — TWINSCAN NXT 1970i/1980i/2050i/2100i (export license required from Sept 2024)
• NVIDIA H100/B200 and equivalent AI chips
• HBM — export restricted
• Advanced EDA software — Cadence, Synopsys, Mentor restricted

What China can still access

• Older DUV machines (pre-restriction models)
• NVIDIA H800 (export-compliant, reduced interconnect)
• Mature node equipment (≥28nm mostly unrestricted)
• Stockpiled ASML DUV machines (hundreds already installed)
• Domestic equipment makers (catching up at mature nodes)

• TSMC makes 90%+ of advanced chips. At 2nm, they’re the only company in volume production. ~$148B revenue projected for 2026.
• ASML is an absolute monopoly. ~230 EUV machines exist on Earth. High-NA ($400M each) unlocks sub-2nm. No competitor for decades.
• CoWoS is the hidden bottleneck. Sold out through 2026. NVIDIA claims >60% of capacity. Google cutting TPU production targets because of it.

• Cost per transistor is now rising. Wafer costs went from $3K (28nm) to $30K (2nm). Design costs hit $724M. The era of cheap transistors is over.
• Reshoring is slow. TSMC Arizona works. Most other projects are delayed or cancelled. Taiwan remains central for 3–5+ more years.
• China finds workarounds. SMIC reached 5nm with DUV at 30–40% yields. Export controls slow but don’t stop progress. The gap is 2–3 generations.
• Geography is destiny — for now. The most advanced AI chips flow through Taiwan, South Korea, and the Netherlands.